1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. In particular, embodiments of the invention relate to a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit.
This application claims priority to Korean Patent Application 10-2005-0131194, filed on Dec. 28, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Generally, standby current in a semiconductor memory device may be current that leaks from a semiconductor memory device while the semiconductor memory device is in a standby mode. Standby current may also be referred to herein as standby leakage current.
An active mode of a semiconductor memory device may be a mode in which peripheral circuits of the semiconductor memory device operate to store data in memory cells of the semiconductor memory device or output data stored in the memory cells to an element(s) outside of the semiconductor memory device. A standby mode of a semiconductor memory device may be a mode in which read and write operations are not performed on the memory cells. In addition, peripheral circuits may be disabled and the amount of power consumed by the peripheral circuits may be reduced while the semiconductor memory device is in the standby mode.
When a semiconductor memory device is in a standby mode for a relatively long amount of time, the semiconductor memory device enters a deep power down mode in order to stop the operation of peripheral circuits to thereby reduce the amount of power consumed by the semiconductor memory device in the standby mode.
FIG. 1A is a timing diagram illustrating timings for an exemplary entry of a conventional semiconductor memory device into a deep power down mode, and FIG. 1B is a timing diagram illustrating timings for an exemplary exit of a conventional semiconductor memory device from the deep power down mode. The deep power down mode will now be described briefly.
The deep power down mode is controlled by an external command. In the semiconductor memory device, after a precharge time tRT elapses (precharge time tRT is initiated in accordance with a precharge command), the semiconductor memory device enters a deep power down mode DPD and then exits deep power down mode DPD in response to a clock signal CLOCK and in accordance with the respective states of signals input through an external signal pin of the semiconductor memory device. The signals may be a chip selection signal CS, a row address strobe /RAS, a column address strobe /CAS, a write enable signal WE, and a clock enable signal CKE.
An exemplary process in which a semiconductor memory device enters and exits deep power down mode DPD will now be described. When chip selection signal CS, clock enable signal CKE, and write enable signal WE each have a logic low level; and row address strobe /RAS and column address strobe /CAS each have a logic high level, the semiconductor memory device enters deep power down mode DPD in response to clock signal CLOCK. Then, regardless of the respective logic levels of chip selection signal CS, row address strobe /RAS, column address strobe /CAS, and write enable signal WE, deep power down mode DPD is completed (i.e., the semiconductor memory device exits deep power down mode DPD) when clock enable signal CKE transitions to a logic high level (see FIG. 1B).
Standby leakage current will now be described using a Static Random Access Memory (SRAM) device as an exemplary semiconductor memory device in which standby leakage occurs.
A unit-memory cell of SRAM is generally configured to store data using a latch comprising two inverters connected with one another. Data may be stored in a memory cell using a bit line pair and may also be output from the memory cell. In addition, bit line pairs are precharged with a voltage having a given level before data is input or output.
FIG. 2 is a circuit diagram illustrating standby leakage current in a portion of a conventional SRAM device. FIG. 2 illustrates a unit-memory cell of an SRAM device, and standby leakage current in the unit-memory cell is represented by arrows.
Standby leakage current in the SRAM device may be divided into gate leakage current (represented by gate leakage current arrows A1) and sub-threshold leakage current (represented by sub-threshold leakage current arrows A2). Referring to transistors PM11, PM12, NM11, NM12, NM13, and NM14 of FIG. 2, a gate leakage current arrow A1 may indicate standby leakage current passing between a drain terminal and a gate terminal, or between a source terminal and a gate terminal, of one of the transistors mentioned previously. A sub-threshold leakage current arrow A2 may indicate standby leakage current flowing between one or more pairs of drain and source terminals.
When the semiconductor memory device partially illustrated in FIG. 2 is in the standby mode, the voltage level apparent on word line WL within the semiconductor memory device has a logic low level, so access transistors NM13 and NM14 are turned OFF. Thus, first and second output terminals N1 and N2 of the first and second inverters illustrated in FIG. 2, which may be storing data, are electrically insulated from bit line pair BL, BLB. The first inverter of FIG. 2 comprises PMOS transistor PM11 and NMOS transistor NM11, and the second inverter of FIG. 2 comprises PMOS transistor PM12 and NMOS transistor NM12.
Then, bit line pair BL, BLB is precharged to a power source voltage VCC by a bit line precharge circuit (not shown). When bit line pair BL, BLB is precharged to a power source voltage VCC, standby leakage current (which is indicated by arrows A1 and A2) flows. The magnitude of the standby leakage current indicated by arrows A1 and A2 is proportional to the magnitude of power source voltage VCC.
In general, power source voltages VCC having various voltage levels are applied to a semiconductor memory device according to strictly defined specifications so as to properly control the device's operating characteristics. The magnitude of standby leakage current (comprising gate leakage current and sub-threshold leakage current) is proportional to the magnitude of power source voltage VCC. When a high level power source voltage HVCC (i.e., a power source voltage VCC having a relatively high voltage level) is applied in the semiconductor memory device, the amount of standby leakage current may increase. Many attempts to reduce the amount of standby leakage current suffered by memory cells based on varying the voltage level of power source voltage VCC have been proposed, as in, for example, U.S. Pat. Nos. 6,970,374; 6,611,451; and 5,764,566. The subject matter of each of the preceding patents is hereby incorporated by reference in its entirety.
Two of the various methods used to reduce standby leakage current will be described herein. The first method is an exemplary method for increasing the threshold voltage Vth of MOS (Metal Oxide Semiconductor) transistors within a memory cell, and the second is a method for differentially controlling the levels of the voltages apparent on respective ground connection terminals Vgnd of memory cells during an active mode and a standby mode, etc. Each ground connection terminal Vgnd may be referred to herein as a virtual ground terminal Vgnd in order to clearly distinguish it from ground voltage VSS.
One shortcoming of this method of increasing the threshold voltage Vth of a MOS transistor in a memory cell is that certain operating characteristics of the memory cell may become impaired when a relatively low external power source voltage LVCC is applied in the semiconductor memory device.
In the method for differentially controlling the level of the voltage apparent on a virtual ground terminal Vgnd of memory cells in an active mode and in a standby mode, virtual ground terminal Vgnd may be set to a voltage level substantially equal to a ground voltage VSS when the semiconductor memory device is in the active mode, and a voltage apparent on virtual ground terminal Vgnd may be set to a voltage level greater than ground voltage VSS when the semiconductor memory device is in the standby mode. Thus, the method may reduce standby leakage current by reducing a power source voltage VCC and reducing a margin between the level of the power source voltage VCC and the level of the voltage apparent on virtual ground terminal Vgnd.
FIG. 3 is a circuit diagram illustrating a portion of an exemplary conventional SRAM device.
Referring to FIG. 3, the SRAM device of FIG. 3 may comprise a memory cell sector 30, a bias sector 32, and a sleep sector 34. Memory cell sector 30 may comprise memory cells adapted to store data. In addition, bias sector 32 controls the voltage level of virtual ground terminal Vgnd when the SRAM device of FIG. 3 is in the standby mode. Bias sector 32 comprises NMOS transistors NM31 to NM34. NMOS transistors NM31 to NM34 receive bias signals bias0 to bias3, respectively, and control an operational resistance apparent in bias sector 32. The operational resistance is calculated in accordance with the level of the voltage apparent on virtual ground terminal Vgnd and the amount of current flowing between drain and source terminals of NMOS transistors NM31 to NM34. The voltage apparent on virtual ground terminal Vgnd is represented herein as the product of a current Ioff, which is the current flowing between source and drain terminals of NMOS transistors NM31 to NM34 when the SRAM device is in a standby mode, and the operational resistance of NMOS transistors NM31 to NM34.
That is, the voltage apparent on virtual ground terminal Vgnd may be expressed as Vgnd=Ioff*Rbias_on, wherein Rbias_on represents the operational resistance of NMOS transistors NM31 to NM34.
Sleep sector 34 is controlled in accordance with a sleep signal Sleep, and comprises a sleep transistor NM35 that is turned ON when the memory cell sector is in an active mode and is turned OFF when the memory cell sector is in a standby mode.
As described above, the SRAM device partially illustrated in FIG. 3 may reduce standby leakage current by controlling the voltage level apparent on virtual ground voltage Vgnd through bias sector 32.
In addition, various mobile applications require very low standby leakage current. In these applications, the amount of standby leakage current is very sensitive to variations in the fabrication processes used to manufacture the constituent semiconductor device, variations in the applied external power source voltage (i.e., the level of a voltage received form an external power source), and temperature.
However, a limitation in conventional semiconductor memory devices is that conventional semiconductor memory devices do not account for process variation or temperature variation when reducing standby leakage current.
Conventional semiconductor memory devices suffer from problems such as data loss and the consumption of excess power as a result of standby leakage current caused by variations in temperature, external power source voltage, and fabrication process (hereafter “process scatter”).